Process Variation Console

Every parameter on a chip — a threshold voltage, a transistor speed, a line width — varies, and that variation comes from many independent sources: the lithography, the etch, the polish, the irreducible randomness of atoms. The crucial fact about combining them is that they add in quadrature, not linearly. The total variance is the sum of the individual variances, so the total sigma is the root of the sum of squares.

That squaring has a profound practical consequence: the largest source dominates, and small ones barely matter. A source with twice the sigma of another contributes four times the variance. Once you square a small contributor against a large one, it nearly vanishes from the total — which is why trimming minor sources is wasted effort and controlling the dominant one is the whole game. The variance-contribution Pareto here ranks the sources by what actually moves the total, and it's usually more skewed than the raw sigmas suggest.

The combined variation then meets the specification, and that's where parametric yield is decided. If the parameter is normally distributed around its nominal with the combined sigma, the fraction inside the spec window is just the area of that bell curve between the limits — the same mathematics as Cpk. Dies outside the window are defect-free but fail their bin: parametric loss, invisible on a defect map, real at electrical test.

And the same total sigma sets the process corners — the ±3σ extremes designers must close timing and power against. Wider variation pushes the corners out and forces more design margin, costing performance; tighter control pulls them in. So reducing the dominant variation source improves parametric yield and relaxes design margins at once. Take the capability view in the Process Capability console and fold parametric loss into the total in the Yield Predictor.