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Target impedance · IR drop · decoupling · droop budget

Power Delivery Network Console

Delivering a thousand amps at sub-1V is one of the hardest problems in chip design. Compute the target impedance the PDN must beat, the static IR drop against your droop budget, and the decoupling capacitance needed to ride out transient current steps.

01 · Quick estimate

Core voltage, power & PDN resistance → target impedance and IR drop.

Target impedance
0.161
IR drop
47
mV · 6.2%
Droop budget, current & decoupling ↓
02 · Deep analysis

Power-integrity console

Resistance vs target
6.2%IR / Vdd
PDN 0.050 mΩ vs target 0.161 mΩ — within budget
Max current
933 A
Transient step
467 A
Droop budget
75 mV
10% of 0.75V
Decap (bulk)
31 µF
for 5ns step
Droop budget · 75 mV allowed
Static IR drop47 mV

Static IR drop uses 62% of the droop budget — the rest must absorb di/dt transients, which is what the target impedance and decap control.

PDN within budget · target 0.161

At 0.75V the 700W load draws 933A, so the PDN must stay below 0.161 mΩ to hold droop within 75mV. Your 0.050 mΩ network has 0.111 mΩ of margin.

Drill into a specific conductor in the Voltage Drop console; set the current from the Power Budget console.

Why it matters

Why power delivery is a frontier problem

Low voltage means brutal currents

As core voltage falls toward 0.7V while power climbs to a kilowatt, the current rockets past a thousand amps. Every milliohm of resistance then becomes tens of millivolts of drop — on a budget of only ~75mV.

Target impedance is the PDN's pass/fail line

The allowable droop divided by the transient current step gives a target impedance the network must stay below across all frequencies. Beat it and the rail is stable; exceed it anywhere and the core browns out.

Decoupling capacitors are the fast reservoir

The voltage regulator is far too slow for nanosecond current steps. Decap supplies that transient charge locally until the regulator catches up — sizing it correctly is what keeps droop within budget during sudden load swings.

Backside power delivery exists for this reason

Routing power through the back of the wafer (BSPDN) shortens the path and cuts resistance and inductance, directly attacking IR drop and di/dt noise — one of the biggest reasons the industry is adopting it at the leading edge.

Field notes

A thousand amps under a volt

The hardest electrical problem in a modern chip isn't switching the transistors — it's feeding them. As core voltages dropped toward 0.7V to save energy and power climbed toward a kilowatt, the current required exploded past a thousand amps, and delivering that much current at that low a voltage, cleanly, through a network of planes, vias, bumps and on-die wires, is a genuine frontier of engineering.

Two effects threaten the rail. The static one is IR drop: current times the network's resistance. At a thousand amps, a mere twentieth of a milliohm already costs fifty millivolts — and the entire droop budget might be only seventy-five. The dynamic one is di/dt: when the load slams current up or down in nanoseconds, the network's inductance throws a voltage spike on top. Together they must stay within a budget that is a small single-digit percentage of the supply, or the circuits slow down and fail.

The unifying design metric is target impedance: the allowable droop divided by the transient current step. The PDN must keep its impedance below that target not just at DC (where IR drop lives) but across the whole frequency range up to hundreds of megahertz (where di/dt lives). Decoupling capacitors are the trick that makes it possible — they form a fast local reservoir that supplies transient current until the comparatively sluggish voltage regulator can respond, and sizing them across a frequency hierarchy is much of the art.

This is why backside power delivery — routing the power network through the back of the wafer to shorten the path — is one of the most consequential leading-edge innovations: it directly cuts the resistance and inductance that this console quantifies. Set the current from the Power Budget console, drill into a specific conductor's IR drop and electromigration in the Voltage Drop console, and remember the PDN's own losses become heat for the thermal tools.

Power Delivery Network FAQs

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Trusted by Power-Integrity & SoC Teams

4.8
Based on 2,970 reviews

Target impedance = droop ÷ current step is the first number on any PDN spec, and this computes it cleanly alongside static IR drop. Showing that a sub-volt kilowatt part needs a sub-0.1-milliohm target makes the difficulty visceral. The decap estimate is a sane starting point.

D
Dr. Vikram Nair
Power-integrity engineer
June 7, 2026

The low-voltage-means-huge-current framing is exactly what I use to justify backside power delivery to architects. IR drop as a percentage of Vdd against the droop budget is the pass/fail I report. Pairs perfectly with the voltage-drop tool for the conductor detail.

C
Claire Dubois
Board/package PI lead
April 28, 2026

Clean target-impedance and IR-drop math with realistic presets. The 2,000A figure for a 0.7V megachip lands hard. Would love an impedance-vs-frequency profile, but as a first-order PDN spec tool it's exactly right.

H
Hideo Yamada
SoC power architect
March 8, 2026

I set the target impedance here before building the impedance profile in simulation. The decap sizing and droop-budget breakdown match my hand calcs. The backside-power-delivery context is the conversation our whole field is having.

A
Amara Diallo
Hardware power integrity
December 30, 2025

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target impedance = allowed droop ÷ transient step · IR drop = current × resistance · decap ≈ step × time ÷ droop · Last reviewed: 2026-06