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Cost per good die · live P&L · margin against ASP

Wafer Cost Console

The cost dashboard that prices a chip. It divides wafer cost by net good dies (gross × yield), stacks on packaging, test and amortized NRE, and — against your ASP — shows gross margin and break-even volume, live as you adjust.

01 · Quick estimate

Wafer cost ÷ (dies × yield) → cost per good die.

Cost / good die
$34.44
608 net good · silicon $27.14
71%MARGIN
Full cost stack & margin ↓
02 · Deep analysis

Cost stack & margin console

Cost stack vs ASP
$34.44/die
Silicon$27.14
Packaging$1.50
Test$0.80
NRE$5.00
Total cost per good die
$34.44
608 net good dies/wafer · NRE $5.00/die
Gross margin
71%
Profit / die
$85.56
Break-even volume (recover NRE)
276,055 units
Excellent margin

A wide gross margin — strong pricing power or a very efficient cost stack. Fabless-IP-leader territory.

Biggest line: silicon at $27.14 (79% of cost).

Next: model the program P&L over volume in Chip Profitability.

Reference

Wafer price & mask cost by node

NodeWafer (300mm)Mask setNRE/die @ 1M
28nm$3,000$2M$2.00
16nm$6,000$6M$6.00
7nm$10,000$15M$15.00
5nm$16,500$25M$25.00
3nm$20,000$35M$35.00
2nm$30,000$50M$50.00

Gross dies from the Die Per Wafer console; yield from the Yield console.

Why it matters

The economics behind the number

A 3nm wafer costs roughly $20,000

versus ~$3,000 at 28nm. Each node buys more transistors but the wafer climbs steeply, so cost-per-transistor only improves if your die shrinks and yields well — node migration is an economic decision, not just a technical one.

A leading-edge mask set can exceed $30M

at 3nm. That NRE amortizes across volume: at 1M units it adds $30/die, at 100M units just $0.30. Low-volume chips on bleeding-edge nodes are crushed by NRE — which is why many stay on mature nodes.

Yield sits in the denominator

cost-per-good-die = wafer cost ÷ (gross dies × yield). At 80% yield a $15,000 wafer with 700 dies is ~$26.80/die; at 50% yield ~$42.90/die. Yield improvement is often the cheapest cost-down available.

Packaging is now a major cost line

for AI silicon — advanced packaging (CoWoS, HBM) can rival or exceed the silicon cost of an accelerator, which is why this console treats packaging and test as first-class terms.

Field notes

Cost per chip: where strategy meets arithmetic

Every chip strategy decision — which node, what die size, monolithic or chiplet, which volume to commit — resolves to one number: the cost of one working chip. The arithmetic is simple; the inputs hide most of the industry's hardest trade-offs, and getting them wrong is how products miss margin or never recover their design cost.

The spine is one division: cost per good die = wafer cost ÷ net good dies, where net good dies is gross dies × yield. The subtlety is "good." You pay for the whole wafer regardless of how many work, so a $16,500 wafer holding 760 dies costs far more than $21.71/chip once yield enters — at 80% only 608 are sellable, so each costs $27.14. Forgetting to divide by yield is the most common and expensive mistake in chip costing.

On top sit three terms modern designs can't ignore. Packaging has exploded for AI silicon — CoWoS and HBM can rival the logic die. Test adds real ATE-time dollars. And NRE — one-time design and mask cost — has grown so steep at the leading edge that it reshapes which products can use which nodes. A 3nm mask can exceed $30M, and because NRE amortizes across volume, it's $30/die at a million units and thirty cents at a hundred million.

Use it as the capstone of the cost trio: Die Per Wafer supplies gross dies, Yield the working fraction, and this turns them into cost, margin and break-even — the language executives decide in.

Wafer Cost FAQs

Have more questions? Contact us

Trusted by Product, Finance & BD Teams

4.8
Based on 4,150 reviews

This is the model I bring to pricing reviews now. Silicon, packaging, test and NRE in one live bar with margin against ASP — it ends the 'what does this chip actually cost' debate in minutes. The node presets are a great starting point.

J
Jonathan Reyes
Director of product, fabless SoC
May 2, 2026

NRE amortization and break-even are exactly what I need for program P&L. Watching cost-per-die collapse as I raise volume makes the 'leading-edge needs scale' argument self-evident. Pairs perfectly with die-per-wafer and yield.

M
Mei Ling Chua
Semiconductor financial analyst
March 28, 2026

I quote customers with this open. Plug volume and target ASP and the break-even and margin tell us instantly whether a node makes sense. The mask-cost reality anchors have saved customers from taping out low-volume on 3nm.

A
Andreas Kohl
ASIC business development
February 11, 2026

As a finance lead without deep process background, the live breakdown finally made chip cost legible. Would love a multi-year ramp, but for unit economics and break-even it's a staple in our board deck.

F
Fatima Al-Rashid
Hardware startup CFO
December 20, 2025

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cost/good die = wafer cost ÷ (gross dies × yield) + packaging + test + NRE/volume · Last reviewed: 2026-06