Semiconductor CapEx Console

The defining economic fact of modern semiconductors is the size of the entry ticket. Building the capacity to make leading-edge chips costs tens of billions, and that number has climbed faster than almost anything in industrial history — a wall of capital that reshaped who can compete and why governments treat chip manufacturing as national infrastructure.

The right way to compare fabs of different sizes is capital intensity: the capex per unit of capacity, in dollars per wafer-per-month. It strips out fab size and reveals the underlying cost of adding capacity at a node. That figure has risen ~five-fold from 28nm to 2nm — not from waste, but because each node demands more process steps, tighter tolerances, and above all more EUV lithography, the single most expensive category in any advanced fab.

EUV is why the breakdown looks the way it does — at the leading edge, lithography alone is a third or more of the entire tool-and-facility bill, dwarfing etch, deposition and metrology. The cleanroom and facility, perhaps a fifth of the build, are a large fixed cost incurred before any tool arrives, which is exactly why brownfield expansion is so much cheaper than greenfield.

This capital becomes per-wafer cost through depreciation — written down over just five to eight years because the node becomes obsolete quickly. Pair this with the Fab ROI console to turn a capex estimate into a return, and with Wafer Cost to see how that capital flows into a single chip's price.