Node Migration Console
Migrating to a smaller node shrinks the die and improves performance and power — but the wafer costs more, and at the leading edge it can cost more per chip despite the shrink. Pick two nodes and the full PPAC trade-space and the decisive cost-per-chip ratio update live.
From node → to node. The cost-per-chip ratio is the verdict.
7nm → 5nm PPAC console
Cost per chip rises despite the shrink. Only migrate if the performance or power gain is worth the premium for your product.
Wafer price +65% while density +52%. Net: each chip costs +9% more despite being smaller. EUV: partial → full.
Next: turn the chosen node into a per-chip cost in Wafer Cost.
The node database
| Node | Density | Wafer | Perf | Power | EUV |
|---|---|---|---|---|---|
| 28nm | 3.9 MTr/mm² | $3,000 | 1.00× | 1.00× | — |
| 16/14nm | 28 MTr/mm² | $6,000 | 1.40× | 0.50× | — |
| 10nm | 52 MTr/mm² | $6,000 | 1.68× | 0.30× | — |
| 7nm | 91 MTr/mm² | $10,000 | 2.02× | 0.18× | partial |
| 5nm | 138 MTr/mm² | $16,500 | 2.32× | 0.13× | full |
| 3nm | 197 MTr/mm² | $20,000 | 2.55× | 0.09× | full |
| 2nm | 313 MTr/mm² | $30,000 | 2.81× | 0.07× | full |
The economics behind node migration
For decades each node made transistors cheaper. From ~7nm onward, wafer prices and mask costs rose so steeply that cost-per-transistor flattened — and for some migrations increased. This console quantifies that break in Moore's-Law economics for your nodes.
EUV scanners (~$150–400M each) entered volume at 7nm and dominate 5nm/3nm. They simplify some steps but add enormous capital and per-wafer cost — which is why the wafer-price jump from 16nm to 5nm is far steeper than the density gain alone.
Design and NRE escalate with each node, so migrating isn't just a higher wafer price — it's a much larger upfront bet that pays back only at high volume. A node that's cheaper per chip can still be the wrong move for a low-volume product.
GAA nanosheet transistors and backside power delivery at 2nm restore meaningful PPAC scaling, but at the highest wafer price yet (~$30k). The gains are real; the economics demand serious volume.
Node migration stopped being automatic
For most of the industry's history the node decision was easy: move to the newest process you could afford, because each generation made transistors smaller, faster, lower-power AND cheaper. That last word quietly stopped being true around 7nm, and the consequences reshaped the business. Today the node decision is a genuine trade-off.
The framework is PPAC, and the trap is looking at one axis alone. A newer node reliably improves the first three — the die shrinks with density, performance rises at iso-power, energy per operation falls. The catch is the fourth: cost per chip depends on a wafer that got more expensive versus a wafer that now yields more (smaller) dies, and at the leading edge the wafer-price increase has begun to outrun the density gain.
One ratio captures it: (new wafer ÷ old wafer) × (old density ÷ new density). Run 7nm→5nm and you get ~1.65 × 0.66 ≈ 1.09 — a 9% cost increase per chip despite a third smaller die. Run 28nm→16nm and you get ~0.28 — a 72% decrease, the old-era win. Same formula, opposite conclusions, all about whether density scaling outpaced wafer price.
What changed was largely EUV and escalating mask cost. That economics explains the behavior that looks irrational until you do the math — huge successful product lines deliberately staying on mature nodes. Use this console to quantify the trade-off, then turn the chosen node into a full business case with Wafer Cost and Chip Profitability.
Trusted by Architecture, Strategy & Analyst Teams
“The cleanest articulation of the node decision I've seen in a browser. The cost-per-chip ratio going ABOVE 1 for some migrations finally makes the 'why aren't we on the latest node' conversation honest with leadership. The PPAC radar is exec-ready.”
“I sanity-check foundry roadmap claims against cost reality with this. Watching cost-per-transistor flatten from 7nm onward, quantified for specific node pairs, is exactly the Moore's-Law-economics story I write about.”
“The area-shrink and power-reduction numbers match what we see porting blocks between nodes. Pairs perfectly with the wafer-cost and profitability consoles for a full migration business case.”
“Confirmed quantitatively why our long-life automotive parts stay on mature nodes — the migration cost ratio is well above 1 and we don't need the performance. As a decision tool it's excellent.”
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cost-per-chip ratio = (wafer_new ÷ wafer_old) × (density_old ÷ density_new) · industry estimates · Last reviewed: 2026-06