HBM Cost Estimator Console
High Bandwidth Memory is a 3D stack of DRAM core dies on a base logic die, and it's often the single most expensive part of an AI accelerator. Estimate the per-stack cost, bandwidth, capacity and power across HBM2E through HBM4 — bandwidth comes from the bus width, capacity from the stack height, and cost from both, divided by a yield that falls as the stack grows.
Generation & stack height → cost, bandwidth and capacity per stack.
Today's leading edge — ~1.2 TB/s/stack, 24–36 GB at 8–12-Hi.
HBM3E 8-Hi stack console
Stack yield 93% (falls with height) — subtotal $222 ÷ yield = $238 per good stack.
8 × HBM3E stacks deliver 9.83 TB/s aggregate bandwidth and 192 GB for $1,906 of memory — frequently more than the logic die itself.
Model the interposer that carries these stacks in the CoWoS Cost console.
Bandwidth is set by the bus width and pin speed, not the stack height — taller stacks add capacity, not bandwidth.
Why HBM dominates AI memory cost
Four to eight HBM stacks at $200–600 each routinely total more than the logic die's manufacturing cost. For many accelerators the bill of materials is a memory story, not a compute one.
An HBM stack bonds 8–16 DRAM core dies onto a base logic die with thousands of TSVs. It's the canonical 3D-stacked device — its yield falls with stack height, exactly like any die stack.
HBM trades clock speed for width: a 1024-bit (HBM3) or 2048-bit (HBM4) interface running at moderate speeds delivers terabytes per second — far more than a narrow, fast GDDR bus, at much better energy per bit.
Only a handful of vendors make HBM, and qualifying it onto a CoWoS package is hard. HBM allocation — alongside CoWoS capacity — has repeatedly been the real limit on how many accelerators ship.
The memory that feeds the AI boom
An AI accelerator is, in a real sense, a memory-bandwidth machine wrapped around some compute. Large models are limited far more by how fast they can move weights and activations than by raw arithmetic, and the technology that supplies that bandwidth is High Bandwidth Memory. It is also, surprisingly often, the most expensive component in the package — a fact that reshapes how the whole bill of materials is understood.
HBM's trick is geometry. Instead of a narrow, blisteringly fast bus like GDDR, it uses an enormously wide one — 1024 bits in HBM3, doubled to 2048 in HBM4 — running at moderate speeds, and it sits millimeters from the processor on a shared interposer rather than centimeters away on the board. That width and proximity deliver terabytes per second per stack at far better energy per bit than any board-level memory could. The price is manufacturing complexity: each stack is a 3D IC, bonding 8 to 16 DRAM core dies onto a base logic die through thousands of through-silicon vias.
Two numbers that people constantly conflate are bandwidth and capacity, and HBM separates them cleanly. Bandwidth is fixed by the bus width and pin speed of the generation — it does not change when you stack more dies. Capacity is set by the stack height: an 8-Hi stack holds two-thirds the gigabytes of a 12-Hi but delivers exactly the same gigabytes per second. So choosing a taller stack buys capacity, not speed, at a cost that rises faster than linearly because stack yield falls with every added die.
That cost matters because accelerators use many stacks — five or six on an H100, eight on an H200 or MI300 — so the memory total runs into the thousands of dollars and frequently exceeds the logic die's manufacturing cost. Combined with the fact that only a few vendors make HBM and each stack must be qualified onto a CoWoS package, HBM has been one of the genuine bottlenecks of the AI build-out. Model the per-stack economics here, then carry the stacks onto their interposer in the CoWoS Cost console and weigh the 3D stacking itself in the 3D IC console.
Trusted by Memory Architects & AI Hardware Teams
“The separation of bandwidth (bus × speed) from capacity (stack height) is the thing people constantly conflate, and this makes it unmistakable. The per-generation comparison maps cleanly to HBM3/3E/4 datasheets, and the yield-falls-with-height curve matches our stacking data.”
“I use this with the CoWoS tool to build accelerator BOMs. Seeing eight HBM3E stacks total more than the GPU die — with the breakdown right there — is the slide that explains AI hardware economics to leadership in one shot.”
“The bandwidth-per-watt comparison across generations is exactly the metric we negotiate on. HBM4's efficiency story is clear here. Pairs perfectly with the 3D IC and CoWoS calculators for the full packaging picture.”
“Great for first-order HBM BOM and bandwidth math. The stack-height-vs-capacity-vs-cost trade-off is well captured. Would love vendor-specific pricing presets, but as a generation-level estimator it's excellent.”
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bandwidth = bus width × pin speed ÷ 8 · capacity = height × per-die GB · cost = (cores×height + base + TSV + assembly) ÷ stack yield · Last reviewed: 2026-06