Transistor Count Console
Bound a chip's size before layout. Sum logic (cores), cache (6 transistors per bit) and accelerators into a transistor budget, then estimate the die area from the node's density — with the cache-vs-logic split laid bare.
Cores, cache & node → transistor count and die area.
5nm: ~140 MTr/mm²
Transistor-budget console
Cache is 70% of the transistor budget — at 256MB, that's 12.3B transistors (6 per bit).
Same design, denser node → smaller die (logic). SRAM scales slowly, so cache-heavy designs shrink less.
This architecture is 17.5B transistors — 70% cache — estimated at 125 mm² on 5nm. Cache dominates — consider stacked/off-die cache to free leading-edge logic area.
Get a precise cache area in the SRAM Area console; turn die area into cost in Wafer Cost.
Why the transistor budget comes first
Each SRAM bit takes six transistors, so a large cache can be most of a chip's transistors — a server CPU is often 60–70% cache by transistor count, even though logic gets the design attention.
Die area is transistors divided by density, and area drives cost (and yield). Estimating the transistor budget early — before layout — is how architects bound the chip's size and price.
Newer nodes pack more transistors per mm² (about 90 at 7nm to 280 at 2nm GAA), so the same design shrinks each generation — the engine of Moore's-law cost reduction, for logic at least.
Logic keeps shrinking, but SRAM bitcells have nearly stalled below 5nm. So cache takes a growing share of die area each node — a major reason for stacked cache (3D V-Cache) and on-package memory.
Counting before drawing
Long before there's any RTL or layout, an architect needs to know roughly how big a chip will be — because size sets cost, yield, and whether the design is even feasible at a target node. The starting point is the transistor budget, and it's built from three blocks: the logic in the cores, the cache, and the accelerators. Sum them, divide by the node's density, and you have a first-order die area to reason about.
The surprise for newcomers is how much of that budget is cache. Each SRAM bit needs six transistors, and modern processors carry tens to hundreds of megabytes, so the cache term routinely exceeds the logic — a server CPU can be two-thirds cache by transistor count even though the cores get nearly all the design attention. Seeing that split is often what motivates moving cache off the expensive logic die.
Node density turns transistors into area, and it's the engine of Moore's-law economics: roughly ninety million transistors per square millimeter at 7nm rising past 280 million at 2nm. The same design shrinks each generation, lowering cost and power — for logic. The catch, and it's a big one, is that SRAM has nearly stopped scaling below 5nm. So cache occupies a growing share of die area at each new node, which is precisely why stacked cache and on-package memory have become central to advanced design.
This console is the back-of-envelope that bounds the chip early. Refine the cache term with the SRAM Area console, get a fuller die estimate in the Die Area console, and turn the result into cost and yield in the Wafer Cost console.
Trusted by Architects & Physical Design Teams
“The logic/cache/accelerator transistor split with a die-area estimate is exactly the back-of-envelope I do at architecture kickoff. Seeing our server CPU come out 70% cache by transistors makes the case for off-die cache instantly. Node density to area is the right first-order model.”
“Cache-dominates-the-budget and SRAM-has-stopped-scaling are the two facts that drive our floorplan, and this surfaces both. The 3nm-vs-5nm die-area comparison frames our node decision. Pairs perfectly with the SRAM-area and die-area tools.”
“Clean transistor budgeting from architecture specs with node-density area. The cache-share callout is the insight leadership needs for the memory strategy. Would love separate logic/SRAM density, but as an early-exploration tool it's exactly right.”
“Bounding die area from transistor count before layout saves weeks of false starts. The accelerator term matters for our AI blocks. Feeds straight into the wafer-cost tool for the price picture. Fast and accurate.”
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transistors = cores×MTr + cache MB×8e6×6 + accel · die area = transistors ÷ density (MTr/mm²) · Last reviewed: 2026-06